View TE28F008B3B120_6230970.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e preliminary ma y 1997 order number: 290605-001 n flexible smartvoltage technology ? 2.7v C3.6v program/erase ? 2.7v?3.6v read operation ? 12v v pp fast production programming n 2.7v or 1.8v i/o option ? reduces overall system power n optimized block sizes ? eight 8-kbyte blocks for data, top or bottom locations ? up to thirty-one 64-kbyte blocks for code n high performance ? 2.7v?3.6v: 120 ns max access time n block locking ? v cc -level control through wp# n low power consumption ? 20 ma maximum read current n absolute hardware-protection ? v pp = gnd option ? v cc lockout voltage n extended temperature operation ? ?40c to +85c n supports code plus data storage ? optimized for fdi, flash data integrator software ? fast program suspend capability ? fast erase suspend capability n extended cycling capability ? 10,000 block erase cycles n automated byte program and block erase ? command user interface ? status registers n sram-compatible write interface n automatic power savings feature n reset/deep power-down ? 1 a i cc typical ? spurious write lockout n standard surface mount packaging ? 48-ball m bga* package ? 40-lead tsop package n footprint upgradeable ? upgradeable from 2-, 4- and 8-mbit boot block n etox? v (0.4 m) flash technology n x8-only input/output architecture ? for space-constrained 8-bit applications the new smart 3 advanced boot block, manufactured on intels latest 0.4 technology, represents a feature- rich solution at overall lower system cost. smart 3 flash memory devices incorporate low volt age capability (2.7v read, program and erase) with high-speed, low-power operation. several new features have been added, including the ability to drive the i/o at 1.8v, which significantly reduces system active power and interfaces to 1.8v controllers. a new blocking scheme enables code and data storage within a single device. add to this the intel-developed flash data integrator (fdi) software and you have the most cost-effective, monolithic code plus data storage solution on the market today. smart 3 advanced boot block byte-wide products will be available in 40-lead tsop and 48-ball bga* packages. additional information on this product family can be obtained by accessing intels www page: http://www.intel.com/design/flcomp smart 3 advanced boot block byte-wide 8-mbit (1024k x 8), 16-mbit (2056k x 8) flash memory family 28f008b3, 28f016b3
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f008b3 and 28f016b3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation 1996, 1997 cg-041493 * third-party brands and names are the property of their respective owners.
e smart 3 advanced boot block Cbyte-wide 3 preliminary contents page page 1.0 introduction .............................................5 1.1 smart 3 advanced boot block flash memory enhancements ..............................5 1.2 product overview.........................................6 2.0 product description..............................6 2.1 package pinouts ..........................................7 2.2 block organization .....................................11 2.2.1 parameter blocks ................................11 2.2.2 main blocks .........................................11 3.0 principles of operation .....................14 3.1 bus operation ............................................14 3.1.1 read....................................................15 3.1.2 output disable.....................................15 3.1.3 standby ...............................................15 3.1.4 deep power-down/reset ....................15 3.1.5 write....................................................15 3.2 modes of operation....................................15 3.2.1 read array ..........................................16 3.2.2 read intelligent identifier .....................17 3.2.3 read status register ..........................17 3.2.4 program mode.....................................18 3.2.5 erase mode .........................................19 3.3 block locking.............................................26 3.3.1 v pp = v il for complete protection .......26 3.3.2 wp# = v il for block locking................26 3.3.3 wp# = v ih for block unlocking ............26 3.4 v pp program and erase voltages ..............26 3.5 power consumption ...................................26 3.5.1 active power .......................................26 3.5.2 automatic power savings (aps) .........27 3.5.3 standby power ....................................27 3.5.4 deep power-down mode.....................27 3.6 power-up/down operation.........................27 3.6.1 rp# connected to system reset ........27 3.6.2 v cc , v pp and rp# transitions .............27 3.7 power supply decoupling ..........................28 3.7.1 v pp trace on printed circuit boards ....28 4.0 absolute maximum ratings ................29 5.0 operating conditions (v ccq = 2.7v C3.6v).......................................29 5.1 dc characteristics: v ccq = 2.7v C3.6v.......30 6.0 operating conditions (v ccq = 1.8v C2.2v).......................................34 6.1 dc characteristics: v ccq = 1.8v C2.2v.......34 7.0 ac characteristics...............................39 7.1 reset operations .......................................43 appendix a: ordering information .................45 appendix b: write state machine current/ next states ..................................................46 appendix c: access time vs. capacitive load...........................................47 appendix d: architecture block diagram ......48 appendix e: additional information ...............49
smart 3 advanced boot block Cbyte-wide e 4 preliminary revision history number description -001 original version
e smart 3 advanced boot block Cbyte-wide 5 preliminary 1.0 introduction this preliminary datasheet contains the specifications for the advanced boot block flash memory family, which is optimized for low power, portable systems. this family of pr oducts features 1.8v C2.2v or 2.vC3.6v i/os and a low v cc /v pp operating range of 2.7vC3.6v for read and program/erase operations. in addition this family is capable of fast programming at 12v. throughout this document, the term 2.7v refers to the full voltage range 2.7vC3.6v (except where noted otherwise) and v pp = 12v refers to 12v 5%. section 1 and 2 provides an overview of the flash memory family including applications, pinouts and pin descriptions. section 3 describes the memory organization and operation for these products. finally, sections 4, 5, 6 and 7 contain the operating specifications. 1.1 smart 3 advanced boot block flash memory enhancements the new 8-mbit and 16-mbit smart 3 advanced boot block flash memory provides a convenient upgrade from and/or compatibility to previous 4- mbit and 8-mbit boot block products. the smart 3 product functions are similar to lower density products in both command sets and operation, providing similar pinouts to ease density upgrades. the smart 3 advanced boot block flash memory features enhanced blocking for easy segmentation of code and data or additional design flexibility program suspend command which permits program suspend to read wp# pin to lock and unlock the upper two (or lower two, depending on location) 8-kbyte blocks v ccq input for 1.8vC2.2v on all i/os. see figures 1C3 for pinout diagrams and v ccq location maximum program time specification for improved data storage. table 1. smart 3 advanced boot block feature summary feature 28f016b3/28f008b3/28f004b3 reference v cc read voltage 2.7vC 3.6v table 9, table 12 v ccq i/o voltage 1.8vC2.2v or 2.7vC 3.6v table 9, table 12 v pp program/erase voltage 2.7vC 3.6v or 11.4vC 12.6v table 9, table 12 bus width 8 bits table 2 speed 120 ns table 15 memory arrangement 1 mbit x 8 (8 mbit), 2 mbit x 8 (16 mbit) blocking (top or bottom) eight 8-kbyte parameter blocks (8/16 mbit) & fifteen 64-kbyte blocks (8 mbit) thirty-one 64-kbyte main blocks (16 mbit) section 2.2 figures 4 and 5 locking wp# locks/unlocks parameter blocks all other blocks protected using v pp switch section 3.3 table 8 operating temperature extended: C40 c to +85 c table 9, table 12 program/erase cycling 10,000 cycles table 9, table 12 packages 40-lead tsop, 48-ball m bga* csp figures 1, 2, and 3
smart 3 advanced boot block Cbyte-wide e 6 preliminary 1.2 product overview intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: v cc for read operation, v ccq for output swing, and v pp for program and erase operation. discrete supply pins allow system desi gners to use the optimal voltage levels for their design. all smart 3 advanced boot block flash memory products provide program/erase capability at 2.7v or 12v and read with v cc at 2.7v. since many designs read from the flash memory a large percentage of the time, 2.7v v cc operation can provide substantial power savings. the 12v v pp option maximizes program and erase performance during production programming. the smart 3 advanced boot block flash memory products are high-performance devices with low power operation. the available densities for the byte-wide devices (x8) are a. 8-mbit (8,388,608-bit) flash memory organized as 1 mbyte of 8 bits each b. 16-mbit (16,777,216-bit) flash memory organized as 2 mbytes of 8 bits each. for word-wide devices (x16) see the smart 3 advanced boot block word-wide flash memory family datasheet. the parameter blocks are located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. the upper two (or lower two) parameter blo cks can be locked to provide complete code security for system initialization c ode. locking and unlocking is controlled by wp# (see section 3.3 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby un- burdening the microprocessor or microcontroller. the status register indicates the status of the wsm by signifying block erase or byte program completion and status. program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the cui. data writes are performed in byte increments. each byte in the flash memory can be programmed independently of other memory locations; every erase operation erases all locations within a block simultaneously. program suspend allows system software to suspend the program command in order to read from any other block. erase suspend allows system software to sus pend the block erase command in order to read from or program data to any other block. the smart 3 advanced boot block flash memory is also designed with an automatic power savings (aps) feature which minimizes system current drain, allowing for very low power designs. this mode is entered immediately following the completion of a read cycle. when the ce# and rp# pins are at v cc , the i cc cmos standby mode is enabled. a deep power- down mode is enabled when the rp# pin is at gnd, minimizing power consumption and providing write protection. i cc current in deep power-down is 1 a typical (2.7v v cc ). a minimum reset time of t phqv is required from rp# switching high until outputs are valid to read attempts. with rp# at gnd, the wsm is reset and status register is cleared. section 3.5 contains additional information on using the deep power-down feature, along with other power consumption issues. the rp# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see section 3.6). refer to the dc characteristics table, sections 5.1 and 6.1, for complete current and voltage specifications. refer to the ac characteristics table, section 7.0, for read, program and erase performance specifications. 2.0 product description this section explains device pin description and package pinouts.
e smart 3 advanced boot block Cbyte-wide 7 preliminary 2.1 package pinouts the smart 3 advanced boot block flash memory is available in 40-lead tsop (see figure 1) and 48- ball m bga packages (see figures 2 and 3). in figure 1, pin changes from one density to the next are circled. both packages, 40-lead tsop and 48- ball m bga package, are 8-bits wide and fully upgradeable across product densities (from 8 mb to 16 mb). advanced boot block 40-lead tsop 10 mm x 20 mm top view 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 21 22 23 24 28f008 28f016 a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we# rp# wp# a 7 a 6 a 5 a 4 a 3 a 2 a 1 v pp a 18 a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we# rp# wp# a 7 a 6 a 5 a 4 a 3 a 2 a 1 v pp a 18 28f008 28f016 a 17 gnd a 10 dq 7 dq 6 dq 5 dq 4 v ccq v cc nc dq 3 dq 2 dq 1 oe# gnd ce# a 0 nc a 17 gnd a 10 dq 7 dq 6 dq 5 dq 4 v ccq v cc nc dq 3 dq 2 dq 1 oe# gnd ce# a 0 a 19 a 19 a 20 dq 0 dq 0 0605-01 figure 1. 40-lead tsop package
smart 3 advanced boot block Cbyte-wide e 8 preliminary a 14 a 12 a 8 v pp wp# nc a 7 a 4 a 15 a 10 we# rp# a 19 a 18 a 5 a 2 a 16 a 13 a 9 a 6 a 3 a 1 a 17 nc d 5 nc d 2 nc ce# a 0 v ccq a 11 d 6 nc d 3 nc d 0 gnd gnd d 7 nc d 4 v cc nc d 1 oe# a b c d e f 1234 567 8 0605-03 note: dotted connections indicate placeholders where there is no solder ball. these connections are reserved for future upgrades. routing is not recommended in this area. figure 2. 8-mbit 48-ball m bga* chip size package
e smart 3 advanced boot block Cbyte-wide 9 preliminary a 14 a 12 a 8 v pp wp# a 20 a 7 a 4 a 15 a 10 we# rp# a 19 a 18 a 5 a 2 a 16 a 13 a 9 a 6 a 3 a 1 a 17 nc d 5 nc d 2 nc ce# a 0 v ccq a 11 d 6 nc d 3 nc d 0 gnd gnd d 7 nc d 4 v cc nc d 1 oe# a b c d e f 1234 567 8 0605-02 note: dotted connections indicate placeholders where there is no solder ball. these connections are reserved for future upgrades. routing is not recommended in this area. figure 3. 16-mbit 48-ball m bga* chip size package
smart 3 advanced boot block Cbyte-wide e 10 preliminary the pin descriptions table details the usage of each device pin. table 2. 16-mbit smart 3 advanced boot block pin descriptions symbol type name and function a 0 Ca 20 input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. 28f008b3: a[0-19], 28f016b3: a[0-20] dq 0 Cdq 7 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. ce# input chip enable: activates the internal control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# inputs. oe# input output enable: enables the devices outputs through the data buffers during an array or status register read. oe# is active low. we# input write enable: controls writes to the command register and memory array. we# is active low. addresses and data are latched on the rising edge of the second we# pulse. rp# input reset/deep power-down: uses two voltage levels (v il , v ih ) to control reset/deep power-down mode. when rp# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to high-z, resets the write state machine, and draws minimum current. when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic-high, the device defaults to the read array mode. wp# input write protect: provides a method for locking and unlocking the two lockable parameter blocks. when wp# is at logic low, the lockable blocks are locked , preventing program and erase operations to those blocks. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [erase] will be set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. see section 3.3 for details on write protection.
e smart 3 advanced boot block Cbyte-wide 11 preliminary table 2. 16-mbit smart 3 advanced boot block pin descriptions (continued) symbol type name and function v ccq input output v cc : enables all outputs to be driven to 2.0v 10% while the v cc is at 2.7v. when this mode is used, the v cc should be regulated to 2.7vC2.85v to achieve lowest power operation (see section 6.1: dc characteristics: v ccq = 1.8vC2.2v). this input may be tied directly to v cc (2.7vC3.6v). see the dc characteristics for further details. v cc device power supply: 2.7vC3.6v v pp program/erase power supply: for erasing memory array blocks or programming data in each block, a voltage of either 2.7vC3.6v or 12v 5% must be applied to this pin. when v pp < v ppl k all blocks are locked and protected against program and erase commands. applying 11.4vC12.6v to v pp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12v for a total of 80 hours maximum (see section 3.4 for details). gnd ground: for all internal circuitry. all ground inputs must be connected. nc no connect: pin may be driven or left floating. 2.2 block organization the smart 3 advanced boot block is an asymmetrically-blocked architecture that enables system integration of c ode and data within a single flash device. each block can be erased independently of the others up to 10,000 times. for the address locations of each block, see the memory maps in figure 4 (top boot blocking) and figure 5 (bottom boot blocking). 2.2.1 parameter blocks the smart 3 advanced boot block flash memory architecture includes parameter blo cks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an eeprom. by using software techniques, the byte- rewrite functionality of eeproms can be emulated. each 8-/16-mbit device contains eight parameter blocks of 8 kbytes (8,192-bytes) each. 2.2.2 main blocks after the parameter blocks, the remai nder of the array is divided into equal size main blo cks for data or code storage. each 16-mbit device contains thirty-one 64-kbyte (65,536-byte) blo cks. each 8-mbit device contains fifteen 64-kbyte blocks.
smart 3 advanced boot block Cbyte-wide e 12 preliminary e0000 dffff d0000 cffff c0000 bffff b0000 affff a0000 9ffff 90000 8ffff 80000 7ffff fffff fe000 fdfff fc000 fbfff f9fff fa000 f7fff 70000 6ffff f8000 f6000 f5fff f4000 f2000 f1fff f0000 effff 64-kbyte block 64-kbyte block 3ffff 30000 2ffff 20000 3 0 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 20 21 22 18 19 17 16 15 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 10 8 9 7 6 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 14 13 12 11 8-mbit advanced boot block 64-kbyte block 64-kbyte block 50000 4ffff 40000 64-kbyte block 64-kbyte block 1ffff 10000 0ffff 00000 0 1 2 4 5 f3fff 5ffff 60000 1e0000 1bffff 0d0000 0cffff 0c0000 0bffff 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 1fffff 1fe000 1fdfff 1fc000 1fbfff 1f9fff 1fa000 1f7fff 070000 06ffff 1f8000 1f6000 1f5fff 1f4000 1f2000 1f1fff 1f0000 1effff 64-kbyte block 64-kbyte block 03ffff 030000 02ffff 020000 3 0 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 8-kbyte block 36 37 38 34 35 33 32 31 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 10 8 9 7 6 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 30 29 12 11 16-mbit advanced boot block 64-kbyte block 64-kbyte block 050000 04ffff 040000 64-kbyte block 64-kbyte block 01ffff 010000 00ffff 000000 0 1 2 4 5 1f3fff 05ffff 060000 15ffff 150000 14ffff 140000 13ffff 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 19 17 18 16 15 64-kbyte block 64-kbyte block 21 20 64-kbyte block 64-kbyte block 0e0000 0dffff 13 14 0effff 0f0000 1b0000 1a0000 19ffff 1affff 64-kbyte block 64-kbyte block 28 27 190000 180000 17ffff 18ffff 64-kbyte block 64-kbyte block 26 25 170000 64-kbyte block 160000 16ffff 64-kbyte block 64-kbyte block 22 23 24 1dffff 1d0000 1cffff 1c0000 0605-05 figure 4. 8-/16-mbit advanced boot block byte-wide top boot memory maps
e smart 3 advanced boot block Cbyte-wide 13 preliminary 70000 6ffff 60000 5ffff 50000 4ffff 40000 3ffff 30000 2ffff 20000 1ffff 10000 0ffff fffff f0000 effff e0000 dffff cffff d0000 bffff 0e000 0dfff c0000 b0000 affff a0000 90000 8ffff 80000 7ffff 8-kbyte block 8-kbyte block 07fff 06000 05fff 04000 3 0 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 20 21 22 18 19 17 16 15 64-kbyte block 8-kbyte block 64-kbyte block 8-kbyte block 64-kbyte block 10 8 9 7 6 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 14 13 12 11 8-mbit advanced boot block 8-kbyte block 8-kbyte block 0a000 09fff 08000 8-kbyte block 8-kbyte block 03fff 02000 01fff 00000 0 1 2 4 5 9ffff 0bfff 0c000 170000 14ffff 060000 05ffff 050000 04ffff 040000 03ffff 030000 02ffff 020000 01ffff 010000 00ffff 1fffff 1f0000 1effff 1e0000 1dffff 1cffff 1d0000 1bffff 00e000 00dfff 1c0000 1b0000 1affff 1a0000 190000 18ffff 180000 17ffff 8-kbyte block 8-kbyte block 007fff 006000 005fff 004000 3 0 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 36 37 38 34 35 33 32 31 64-kbyte block 8-kbyte block 64-kbyte block 8-kbyte block 64-kbyte block 10 8 9 7 6 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 30 29 12 11 16-mbit advanced boot block 8-kbyte block 8-kbyte block 00a000 009fff 008000 8-kbyte block 8-kbyte block 003fff 002000 001fff 000000 0 1 2 4 5 19ffff 00bfff 00c000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 0b0000 0affff 0a0000 09ffff 090000 08ffff 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 19 17 18 16 15 64-kbyte block 64-kbyte block 21 20 64-kbyte block 64-kbyte block 070000 06ffff 13 14 07ffff 080000 140000 130000 12ffff 13ffff 64-kbyte block 64-kbyte block 28 27 120000 110000 10ffff 11ffff 64-kbyte block 64-kbyte block 26 25 100000 64-kbyte block 0f0000 0fffff 64-kbyte block 64-kbyte block 22 23 24 16ffff 160000 15ffff 150000 0605-06 figure 5. 8-/16-mbit advanced boot block byte-wide bottom boot memory maps
smart 3 advanced boot block Cbyte-wide e 14 preliminary 3.0 principles of operation flash memory combines eeprom functionality with in-circuit electrical program and erase capability. the smart 3 advanced boot block flash memory family utilizes a command user interface (cui) and automated algorithms to simplify program and erase operations. the cui allows for 100% cmos-level control inputs, fixed power supplies during erasure and programming, and maximum eeprom compatibility. when v pp < v pplk , the device will only execute the following commands successfully: read array, read status register, clear status register and read intelligent identifier. the device provides standard eeprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui. in addition, 2.7v or 12v on v pp allows program and erase of the device. all functions associated with altering memory contents, namely program and erase, are accessible via the cui. the internal write state machine (wsm) completely automates program and erase operations while the cui signals the start of an operation and the status register reports status. the cui handles the we# interface to the data and address latches, as well as system status requests during wsm operation. 3.1 bus operation smart 3 advanced boot block flash memory devices read, program and erase in- system via the local cpu or microcontroller. all bus cycles to or from the flash memory conform to standard microcontroller bus cycles. four control pins dictate the data flow in and out of the flash component: ce#, oe#, we# and rp#. these bus operations are summarized in table 3. table 3. bus operations for byte-wide mode mode notes rp# ce# oe# we# wp# a 0 v pp dq 0 C7 read 1,2,3 v ih v il v il v ih xxxd out output disable 2 v ih v il v ih v ih x x x high z standby 2 v ih v ih x x x x x high z deep power-down 2,9 v il x x x x x x high z intelligent identifier (mfr.) 2,4 v ih v il v il v ih xv il x 89 h intelligent identifier (dvc.) 2,4,5 v ih v il v il v ih xv ih x see table 5 write 2,6,7, 8 v ih v il v ih v il xxv pph d in notes: 1. refer to dc characteristics. 2. x must be v il , v ih for control pins and addresses, v pplk , v pph1 or v pph2 for v pp . 3. see dc characteristics for v pplk , v pph1 , v pph2 voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence, a 1 Ca 20 = x 5. see table 5 for device ids. 6. refer to table 6 for valid d in during a write operation. 7. command writes for block erase or byte program are only executed when v pp = v pph1 or v pph2 . 8. to program or erase the lockable blocks, hold wp# at v ih . see section 3.3. 9. rp# must be at gnd 0.2v to meet the maximum deep power-down current specified.
e smart 3 advanced boot block Cbyte-wide 15 preliminary 3.1.1 read the flash memory has three read modes available: read array, read identifier, and read status. these modes are accessible independent of the v pp voltage. the appropriate read mode command must be issued to the cui to enter the corresponding mode. upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control; when active it enables the flash memory device. oe# is the data output (dq 0 Cdq 7 ) control and it drives the selected memory data onto the i/o bus. for all read modes, we# and rp# must be at v ih . figure 14 illustrates a read cycle. 3.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 7 are placed in a high-impedance state. 3.1.3 standby deselecting the device by bringing ce# to a logic- high level (v ih ) places the device in standby mode, which substantially reduces device power consumption. in standby, outputs dq 0 Cdq 7 are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 deep power-down/reset rp# at v il initiates the deep power-down mode, sometimes referred to as reset mode. from read mode, rp# going low for time t plph accomplishes the following: 1. deselects the memory 2. places output drivers in a high-impedance state after return from power-down, a time t phqv is required until the initial memory access outputs are valid. a delay (t phwl or t phel ) is required after return from power-down before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the cui resets to read array mode, and the status register is set to 80h (ready). if rp# is taken low for time t plph during a program or erase operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. after returning from an aborted operation, time t phqv or t phwl /t phel must be met before a read or write operation is initiated respectively. 3.1.5 write a write is any command that alters the contents of the memory array. there are two write commands: program (40h) and erase (20h). writing either of these commands to the internal command user interface (cui) initiates a sequence of internally- timed functions that culminate in the completion of the requested task (unless that operation is aborted by either rp# being driven to v il for of t plrh or an appropriate suspend command). the command user interface does not occupy an addressable memory location. instead, commands are written into the cui using standard microprocessor write timings when we# and ce# are low, oe# = v ih , and the proper address and data (command) are presented. the command is latched on the rising edge of the first we# or ce# pulse, whichever occurs first. figure 15 illustrates a write operation. device operations are selected by writing specific commands into the cui. table 4 defines the available commands. appendix b provides detailed information on moving between the different modes of operation. 3.2 modes of operation the flash memory has three read modes and two write modes. the read modes are read array, read identifier, and read status. the write modes are program and block erase. three additional mode (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. these modes are
smart 3 advanced boot block Cbyte-wide e 16 preliminary reached using the commands summarized in table 4. a comprehensive chart showing the state transitions is in appendix b. 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device will be in the read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any commands being written to the cui. when the device is in the read array mode, four control signals must be controlled to obtain data at the outputs. we# must be logic high (v ih ) ce# must be logic low (v il ) oe# must be logic low (v il ) rp# must be logic high (v ih ) in addition, the address of the desired location must be applied to the address pins. if the device is not in read array mode, as would be the case after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can take place. table 4. command codes and descriptions code device mode description 00 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. ff read array places the device in read array mode, such that array data will be output on the data pins. 40 program set-up this is a two-cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information and initiates the wsm to execute the program algorithm. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 3.2.4. 10 alternate program set-up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will (a) set both sr.4 and sr.5 of the status register to a 1, (b) place the device into the read status register mode, and (c) wait for another command. see section 3.2.5. d0 program resume erase resume/ erase confirm if the previous command was an erase set-up command, then the cui will close the address and data latches, and begin erasing the block indicated on the address pins. if a program or erase operation was previously suspended, this command will resume that operation. during program/erase, the device will respond only to the read status register, program suspend/erase suspend commands and will output status register data when ce# or oe# is toggled.
e smart 3 advanced boot block Cbyte-wide 17 preliminary table 4. command codes and descriptions (continued) code device mode description b0 program suspend erase suspend issuing this command will begin to suspend the currently executing program/erase operation. the status register will indicate when the operation has been successfully suspended by setting either the program suspend (sr.2) or erase suspend (sr.6) and the wsm status bit (sr.7) to a 1 (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip if it is driven to v il . see sections 3.2.4.1 and 3.2.5.1. 70 read status register this command places the device into read status register mode. reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after a program or erase operation has been initiated. see section 3.2.3. 50 clear status register the wsm can set the block lock status (sr.1) , v pp status (sr.3), program status (sr.4), and erase status (sr.5) bits in the status register to 1, but it cannot clear them to 0. issuing this command clears those bits to 0. 90 intelligent identifier puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (a 0 = 0 for manufacturer, a 0 = 1 for device, all other address inputs are ignored). see section 3.2.2. note: see appendix b for mode transition information. 3.2.2 read intelligent identifier to read the manufacturer and device codes, the device must be in read intelligent identifier mode, which can be reached by writing the intelligent identifier command (90h). once in intelligent identifier mode, a 0 = 0 outputs the manufacturers identification code and a 0 = 1 outputs the device code. see table 5 for product signatures. to return to read array mode, write the read array command (ffh). table 5. intelligent identifier table device id size mfr. id -t (top boot) -b ( bottom boot) 8-mbit 89h d2h d3h 16-mbit 89h d0h d1h 3.2.3 read status register the device status register indicates when a program or erase operation is complete, and the success or failure of that operation. to read the status register issue the read status register (70h) command to the cui. this causes all subsequent read operations to output data from the status register until another command is written to the cui. to return to reading from the array, issue the read array (ffh) command. the status register bits are output on dq 0 Cdq 7 . the contents of the status register are latched on the falling edge of oe# or ce#. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation.
smart 3 advanced boot block Cbyte-wide e 18 preliminary when the wsm is active, bit 7 (sr.7) of the status register will indicate the status of the wsm; the remaining bits in the status register indicate whether or not the wsm was successful in performing the desired operation (see table 7). 3.2.3.1 clearing the status register the wsm sets status bits 1 through 7 to 1, and clears bits 2, 6 and 7 to 0, but cannot clear status bits 1 or 3 through 5 to 0. because bits 1, 3, 4, and 5 indicate various error conditions, these bits can only be cleared by the controlling cpu through the use of the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in s equence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note, again, that the read array command must be issued before data can be read from the memory array. 3.2.4 program mode programming is executed using a two-write sequence. the program setup command (40h) is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute the following sequence of internally timed events: 1. program the desired bits of the addressed memory. 2. verify that the desired bits are sufficiently programmed. programming of the memory results in specific bits within an address location being changed to a 0. if the user attempts to program 1s, there will be no change of the memory cell contents and no error occurs. the status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a 0. the status register can be polled by toggling either ce# or oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit sr.4 of the status register is set to indicate a program failure. if sr.3 is set then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted to a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read array mode. 3.2.4.1 suspending and resuming program the program suspend command allows program suspension in order to read data in other locations of memory. once the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). the device continues to output status register data after the program suspend command is written. polling status register bits sr.7 and sr.2 will determine when the program operation has been suspended (both will be set to 1). t whrh1 /t ehrh1 specify the program suspend latency. a read array command can now be written to the cui to read data from blo cks other t han that which is suspended. the only other valid commands, while program is suspended, are read status register and program resume. after the program resume command is written to the flash memory, the wsm will continue with the program process and status register bits sr.2 and sr.7 will automatically be cleared. after the program resume command is written, the device automatically outputs status register data when read (see figure 7, program suspend/resume flowchart). v pp must remain at the same v pp level used for program while in program suspend mode. rp# must also remain at v ih. 3.2.4.2 v pp supply voltage during program v pp supply voltage considerations are outlined in section 3.4.
e smart 3 advanced boot block Cbyte-wide 19 preliminary 3.2.5 erase mode to erase a block, write the erase set-up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. only one block can be erased at a time. the wsm will execute the following sequence of internally timed events to: 1. program all bits within the block to 0. 2. verify that all bits within the block are sufficiently programmed to 0. 3. erase all bits within the block to 1. 4. verify that all bits within the block are sufficiently erased. while the erase sequence is executing, bit 7 of the status register is a 0. when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr.5 of the status register will be set to a 1, indicating an erase error. if v pp was not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr.5 of the status register is set to indicate an erase error, and sr.3 is set to a 1 to identify that v pp supply voltage was not within acceptable limits. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to reset the flash to read array after the erase is complete. 3.2.5.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a predetermined point in the erase algorithm. the status register will indicate if/when the erase operation has been suspended. a read array/program command can now be written to the cui in order to read/write data from/to blocks other t han that which is suspended. the program command can subsequently be suspended to read yet another array location. the only valid commands while erase is suspended are erase resume, program, program resume, read array, or read status register. during erase suspend mode, the chip can be placed in a pseudo-standby mode by taking ce# to v ih . this reduces active current consumption. erase resume continues the erase sequence when ce# = v il . as with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. 3.2.5.2 v pp supply voltage during erase v pp supply voltage considerations are outlined in section 3.4.
smart 3 advanced boot block Cbyte-wide e 20 preliminary table 6. command bus definitions first bus cycle second bus cycle command notes oper addr data oper addr data read array 5 write x ffh intelligent identifier 2,3,5 write x 90h read ia id read status register 5 write x 70h read x srd clear status register 5 write x 50h write (program) 4,5 write x 40h write pa pd alternate write (program) 4,5 write x 10h write pa pd block erase/confirm 5 write x 20h write ba d0h program/erase suspend 5 write x b0h program/erase resume 5 write x d0h address data ba = block address srd = status register data ia = identifier address id = identifier data pa = program address pd = program data x = dont care notes: 1. bus operations are defined in table 3. 2. a 0 = 0 for manufacturer code, a 0 = 1 for device code. 3. following the intelligent identifier command, two read operations access manufacturer and device codes. 4. either 40h or 10h command is valid.
e smart 3 advanced boot block Cbyte-wide 21 preliminary table 7. status register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr.7 write state machine status 1 = ready (wsms) 0 = busy check write state machine bit first to determine byte program or block erase completion, before checking program or erase status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to 1, wsm has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in byte program 0 = successful byte program when this bit is set to 1, wsm has attempted but failed to program a byte. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. the v pp status bit is not guaranteed to report accurate feedback between v ppl k and v pph . sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to 1. pss bit remains set to 1 until a program resume command is issued. sr.1 = block lock status 1 = program/erase attempted on locked block; operation aborted 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr.0 = reserved for future enhancements (r) these bits are reserved for future use and should be masked out when polling the status register.
smart 3 advanced boot block Cbyte-wide e 22 preliminary start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 command program setup program comments data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error 0605-07 figure 6. automated byte programming flowchart
e smart 3 advanced boot block Cbyte-wide 23 preliminary start write b0h read status register bus operation write write no command program suspend read array comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 0 read read array data from block other than the one being programmed. read status register data toggle ce# or oe# to update status register data addr = x standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed write program resume data = d0h addr = x 0605-08 figure 7. program suspend/resume flowchart
smart 3 advanced boot block Cbyte-wide e 24 preliminary start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby command erase setup erase confirm comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted 0605-09 figure 8. automated block erase flowchart
e smart 3 advanced boot block Cbyte-wide 25 preliminary start write b0h read status register bus operation write write no command erase suspend read array comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh/40h read array data/ program array erase completed done reading and/or programming yes write ffh write d0h erase resumed read array data 0 1 0 read read array data from block other than the one being erased. read status register data toggle ce# or oe# to update status register data addr = x standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.6 1 = erase suspended 0 = erase completed write erase resume data = d0h addr = x program program data to block other than the one being erased. 0605-010 figure 9. erase suspend/resume flowchart
smart 3 advanced boot block Cbyte-wide e 26 preliminary 3.3 block locking the smart 3 advanced boot block flash memory architecture features two hardware-lockable parameter blocks so that the kernel c ode for the system can be kept secure while other parameter blocks are programmed or erased as necessary. 3.3.1 v pp = v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. when v pp is below v pplk , any program or erase operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 3.3.2 wp# = v il for block locking the lockable blocks are locked w hen wp# = v il ; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two parameter blocks (blocks #37 and #38 for the 16-mbit, and blo cks #21 and #22 for the 8-mbit) are lockable. for the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 8-/16- mbit) are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 3.3.3 wp# = v ih for block unlocking wp# = v ih unlocks all lockable blocks. these blocks can now be programmed or erased. note that rp# does not override wp# locking as in previous boot block devices. wp# controls all block locking and v pp provides protection against spurious writes. table 8 defines the write protection methods. 3.4 v pp program and erase voltages intels smart 3 products provide in- system programming and erase at 2.7vC3.6v v pp . for customers requiring fast programming in their manufacturing environment, smart 3 advanced boot block includes an additional low-cost, backward-compatible 12v programming feature. the 12v v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12v may be applied to v pp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. table 8. write protection truth table for advanced boot block flash memory family v pp wp# rp# write protection provided xxv il all blocks locked v il xv ih all blocks locked 3 v pplk v il v ih lockable blocks locked 3 v pplk v ih v ih all blocks unlocked 3.5 power consumption while in operation, the flash device consumes active power. however, intel flash devices have a three-tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is idle. if the ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. if rp# = v il the flash enters a deep power-down mode, where current is at a minimum. the combination of these features can minimize overall memory power consumption, and therefore, overall system power consumption. 3.5.1 active power with ce# at a logic-low level and rp# at a logic- high level, the device is in the active mode. refer to the dc characteristics tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices.
e smart 3 advanced boot block Cbyte-wide 27 preliminary 3.5.2 automatic power savings (aps) automatic power savings provides low-power operation during active mode. power reduction control (prc) circuitry allows the flash to put itself into a low current state when not being accessed. after data is read from the memory array, prc logic controls the devices power consumption by entering the aps mode where typical i cc current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. aps reduces active current to standby current levels for 2.7vC3.6v cmos input levels. 3.5.3 standby power with ce# at a logic-high level (v ih ) and the cui in read mode, the flash memory is in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs (dq 0 Cdq 7 ) are placed in a high-impedance state independent of the status of the oe# signal. if ce# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application-specific power and energy requirements. 3.5.4 deep power-down mode the deep power-down mode of the smart 3 advanced boot block products switches the device into a low power savings mode, which is especially important for battery-based devices. this mode is activated when rp# = v il . (gnd 0.2v). during read modes, rp# going low de-selects the memory and places the output drivers in a high impedance state. recovery from the deep power- down state, requires a minimum time equal to t phqv (see ac characteristics table). during program or erase modes, rp# transitioning low will abort the operation, but the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. during deep power-down, all internal circuits are switched to a low power savings mode (rp# transitioning to v il or turning off power to the device clears the status register). 3.6 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp or v cc , powers-up first. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices since the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rp# to the system cpu reset# si gnal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powerg ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode or after v cc transitions above v lko (lockout voltage), is read array mode.
smart 3 advanced boot block Cbyte-wide e 28 preliminary after any program or block erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. refer to ap-617 additional flash data protection using v pp , rp#, and wp# for a circuit-level description of how to implement the protection schemes discussed in section 3.5. 3.7 power supply decoupling flash memorys power switching characteristics require careful device decoupling. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. v pp trace widths and layout should be similar to that of v cc . adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
e smart 3 advanced boot block Cbyte-wide 29 preliminary 4.0 absolute maximum ratings* extended operating temperature during read ............................ C40c to +85c during block erase and program............................ C40c to +85c temperature under bias ......... C40c to +85c storage temperature................... C65c to +125c voltage on any pin (except v cc , v ccq and v pp ) with respect to gnd ............... C0.5v to +5.0v 1 v pp voltage (for block erase and program) with respect to gnd .........C0.5v to +13.5v 1,2,4 v cc and v ccq supply voltage with respect to gnd ............... C0.2v to +5.0v 1 output short circuit current...................... 100 ma 3 notice: this datasheet contains preliminary information on products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is C0.5v on input/output pins. during transitions, this level may undershoot to C2.0v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods < 20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp program voltage is normally 2.7vC3.6v. connection to supply of 11.4vC12.6v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12v for a total of 80 hours maximum. see section 3.4 for details. 5.0 operating conditions (v ccq = 2.7v C3.6v) table 9. temperature and voltage operating conditions 4 symbol parameter notes min max units t a operating temperature C40 +85 c v cc 2.7vC3.6v v cc supply voltage 1,4 2.7 3.6 volts v ccq 2.7vC3.6v i/o supply voltage 1,2,4 2.7 3.6 volts v pp1 program and erase voltage 4 2.7 3.6 volts v pp2 3 11.4 12.6 volts cycling block erase cycling 5 10,000 cycles notes: 1. see dc characteristics tables for voltage range-specific specifications. 2. the voltage swing on the inputs, v in is required to match v ccq . 3. applying v pp = 11.4v C12.6v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12v for a total of 80 hours maximum. see section 3.4 for details. 4. v cc , v ccq and v pp1 must share the same supply when all three are between 2.7v and 3.6v. 5. for operating temperatures of C25 cC +85 c the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles.
smart 3 advanced boot block Cbyte-wide e 30 preliminary 5.1 dc characteristics: v ccq = 2.7v C3.6v table 10. dc characteristics sym parameter notes v cc = 2.7v C3.6v unit test conditions typ max i li input load current 1 1.0 a v cc = v cc max = v cc q max v in = v ccq or gnd i lo output leakage current 1 10 a v cc = v cc max = v cc q max v in = v ccq or gnd i ccs v cc standby current 1,7 20 50 a cmos inputs v cc = v cc max = v ccq max ce# = rp# = v ccq i ccd v cc deep power-down current 1,7 1 10 a cmos inputs v cc = v cc max = v cc q max v in = v cc q or gnd rp# = gnd 0.2v i ccr v cc read current 1,5,7 10 20 ma cmos inputs v cc = v cc max = v cc q max oe# = v ih , ce# =v il f = 5 mhz, i out = 0 ma inputs = v il or v ih i ccw v cc program current 1,4,7 8 20 ma v pp = v pph1 (3v) program in progress 820mav pp = v pph2 (12v) program in progress i cce v cc erase current 1,4,7 8 20 ma v pp = v pph1 (3v) erase in progress 820mav pp = v pph2 (12v) erase in progress i cces v cc erase suspend current 1,2,4,7 20 50 a ce# = v ih erase suspend in progress i ccws v cc program suspend current 1,2,4,7 20 50 a ce# = v ih program suspend in progress i ppd v pp deep power-down current 1 0.2 5 a rp# = gnd 0.2v i ppr v pp read current 1 2 50 a v pp v cc
e smart 3 advanced boot block Cbyte-wide 31 preliminary table 10. dc characteristics (continued) sym parameter notes v cc = 2.7v C3.6v unit test conditions typ max i ppw v pp program current 1,4 15 40 ma v pp = v pph1 (3v) program in progress 10 25 ma v pp = v pph2 (12v) program in progress i ppe v pp erase current 1,4 13 25 ma v pp = v pph1 (3v) erase in progress 825mav pp = v pph2 (12v) erase in progress i ppes v pp erase suspend current 1,4 50 200 a v pp = v pph1 or v pph2 erase suspend in progress i ppws v pp program suspend current 1,4 50 200 a v pp = v pph1 or v pph2 program suspend in progress
smart 3 advanced boot block Cbyte-wide e 32 preliminary table 10. dc characteristics (continued) sym parameter notes v cc = 2.7v C3.6v unit test conditions min max v il input low voltage C0.4 0.4 v v ih input high voltage v ccq C 0.4v v v ol output low voltage 0.10 v v cc = v cc min = v ccq min i ol = 100 m a v oh output high voltage v ccq C 0.1v vv cc = v cc min = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 3 1.5 v complete write protection v pph1 v pp during prog/erase operations 3 2.7 3.6 v v pph2 3,6 11.4 12.6 v v lko v cc program/erase lock voltage 1.5 v v lko2 v ccq program/erase lock voltage 1.2 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25c. 2. i cces and i ccws are specified with device de-selected. if device is read while in erase suspend, current draw is i ccr . if the device is read while in program suspend, current draw is i ccr . 3. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pph1 and v pph2 . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 6. applying v pp = 11.4vC12.6v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12v for a total of 80 hours maximum. see section 3.4 for details. 7. includes the sum of v cc and v ccq current. table 11. capacitance (t a = 25c, f = 1 mhz) sym parameter notes typ max units conditions c in input capacitance 1 6 8 pf v in = 0v c out output capacitance 1 10 12 pf v out = 0v note: 1. sampled, not 100% tested.
e smart 3 advanced boot block Cbyte-wide 33 preliminary test points input output v ccq 0.0 v ccq 2 v ccq 2 0605-011 note: ac test inputs are driven at v ccq for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10%C90%) <10 ns. worst case speed conditions are when v ccq =2.7v. figure 10. 2.7v C3.6v input range and measurement points c l out v ccq device under test r 1 r 2 0605-012 note: see table for component values. figure 11. test configuration test configuration component values for worst case speed conditions test configuration c l (pf) r 1 ( w )r 2 ( w ) 2.7v standard test 50 25k 25k
smart 3 advanced boot block Cbyte-wide e 34 preliminary 6.0 operating conditions (v ccq = 1.8v C2.2v) table 12. temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature C40 +85 c v cc1 2.7vC2.85v v cc supply voltage 1 2.7 2.85 volts v cc2 2.7vC3.3v v cc supply voltage 1 2.7 3.3 volts v ccq 1.8vC2.2v i/o supply voltage 1,4 1.8 2.2 volts v pp1 program and erase voltage 1 2.7 2.85 volts v pp2 1 2.7 3.3 volts v pp3 1,2 11.4 12.6 volts cycling block erase cycling 3 10,000 cycles notes: 1. see dc characteristics tables for voltage range-specific specifications. 2. applying v pp = 11.4v C12.6v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter. v pp may be connected to 12v for a total of 80 hours maximum. see section 3.4 for details. 3. for operating temperatures of C25 cC +85 c the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles. 4. the voltage swing on the inputs, v in is required to match v ccq . 6.1 dc characteristics: v ccq = 1.8v C2.2v these tables are valid for the following power supply combinations only: 1. v cc1 and v ccq and (v pp1 or v pp3 ) 2. v cc2 and v ccq and (v pp2 or v pp3 ) wherever the input voltage v in is mentioned, it is required that v in matches the chosen v ccq .
e smart 3 advanced boot block Cbyte-wide 35 preliminary table 13. dc characteristics: v ccq = 1.8v C2.2v sym parameter notes v cc1 : 2.7vC2.85v v cc2 : 2.7vC3.3v unit test conditions typ max i li input load current 1 1.0 a v cc = v cc max v ccq = v cc q max v in = v ccq or gnd i lo output leakage current 1 10 a v cc = v cc max v ccq = v cc q max v in = v ccq or gnd i ccs v cc standby current 1,7 20 50 a cmos inputs v cc = v cc1 max (2.7vC2.85v) v ccq = v ccq max ce# = rp# = v ccq 150 250 m a cmos inputs v cc = v cc2 max (2.7vC3.3v) v ccq = v ccq max ce# = rp# = v ccq i ccd v cc deep power-down current 1,7 1 10 a cmos inputs v cc = v cc max (v cc1 or v cc2 ) v ccq = v cc q max v in = v cc q or gnd rp# = gnd 0.2v i ccr v cc read current 1,5,7 8 18 ma cmos inputs v cc = v cc1 max (2.7vC2.85v) v ccq = v ccq max oe# = v ih , ce# = v il f = 5 mhz, i out = 0 ma inputs = v il or v ih 12 23 ma cmos inputs v cc = v cc2 max (2.7vC3.3v) v ccq = v ccq max oe# = v ih , ce# = v il f = 5 mhz, i out = 0 ma inputs = gnd 0.2v or v ccq
smart 3 advanced boot block Cbyte-wide e 36 preliminary table 13. dc characteristics: v ccq = 1.8v C2.2v (continued) sym parameter notes v cc1 : 2.7vC2.85v v cc2 : 2.7vC3.3v unit test conditions typ max i ccw v cc program current 1,4,7 8 20 ma v pp = v pph1 or v pph2 program in progress 820mav pp = v pph3 (12v) program in progress i cce v cc erase current 1,4,7 8 20 ma v pp = v pph1 or v pph2 erase in progress 820mav pp = v pph3 (12v) erase in progress i cces v cc erase suspend current 1,2,4,7 20 50 a ce# = v ih erase suspend in progress i ccws v cc program suspend current 1,2,4,7 20 50 a ce# = v ih program suspend in progress i ppd v pp deep power-down current 1 0.2 5 a rp# = gnd 0.2v i ppr v pp read and standby current 1 2 50 a v pp v cc i ppw v pp program current 1,4 15 40 ma v pp = v pph1 or v pph2 program in progress 10 25 ma v pp = v pph3 (12v) program in progress i ppe v pp erase current 1,4 13 25 ma v pp = v pph1 or v pph2 erase in progress 825mav pp = v pph3 (12v) erase in progress i ppes v pp erase suspend current 1 50 200 a v pp = v pph1 , v pph2 , or v pph3 erase suspend in progress i ppws v pp program suspend current 1 50 200 a v pp = v pph1 , v pph2 , or v pph3 program suspend in progress
e smart 3 advanced boot block Cbyte-wide 37 preliminary table 13. dc characteristics: v ccq = 1.8v C2.2v (continued) sym parameter notes v cc1 : 2.7vC2.85v v cc2 : 2.7vC3.3v unit test conditions typ max v il input low voltage C0.2 0.2 v v ih input high voltage v ccq C 0.2v v v ol output low voltage C0.10 0.10 v v cc = v cc min v ccq = v ccq min i ol = 100 m a v oh output high voltage v ccq C 0.1v v v cc = v cc min v ccq = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 3 1.5 v complete write protection v pph1 v pp during prog./erase operations 3 2.7 2.85 v v pph2 3 2.7 3.3 v v pph3 3,6 11.4 12.6 v v lko1 v cc program/erase lock voltage 1.5 v v lko2 v ccq program/erase lock voltage 1.2 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25c. 2. i cces and i ccws are specified with device de-selected. if device is read while in erase suspend, current draw is i ccr . if the device is read while in program suspend, current draw is i ccr . 3. erases and writes inhibited when v pp < v pplk , and not guaranteed outside the valid v pp ranges of v pph1 ,v pph2 . or v pph3. 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 6. applying v pp = 11.4vC12.6v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12v for a total of 80 hours maximum. see section 3.4 for details. 7 includes the sum of v cc and v ccq current table 14. capacitance (t a = 25c, f = 1 mhz) sym parameter notes typ max units conditions c in input capacitance 1 6 8 pf v in = 0v c out output capacitance 1 10 12 pf v out = 0v note: 1. sampled, not 100% tested.
smart 3 advanced boot block Cbyte-wide e 38 preliminary test points input output v ccq 0.0 v ccq 2 v ccq 2 0605-011 note: ac test inputs are driven at v ccq for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10%C90%) <10 ns. for worst case speed conditions v ccq =1.8v. figure 12. 1.8v 2.2v input range and measurement points c l out v ccq device under test r 1 r 2 0605-012 note: see table for component values. figure 13. test configuration test configuration component values for worst case speed conditions test configuration c l (pf) r 1 ( w )r 2 ( w ) 1.8v standard test 50 16.7k 16.7k note: c l includes jig capacitance.
e smart 3 advanced boot block Cbyte-wide 39 preliminary 7.0 ac characteristics ac characteristics are applicable to both v ccq ranges. table 15. ac characteristics: read operations (extended temperature) load c l = 50 pf # symbol parameter v cc 2.7v C3.6v 4 units prod 120 ns 150 ns notes min max min max r1 t avav read cycle time 120 150 ns r2 t avqv address to output delay 120 150 ns r3 t elqv ce# to output delay 2 120 150 ns r4 t glqv oe# to output delay 2 65 65 ns r5 t phqv rp# to output delay 600 600 ns r6 t elqx ce# to output in low z 3 0 0 ns r7 t glqx oe# to output in low z 3 0 0 ns r8 t ehqz ce# to output in high z 3 40 40 ns r9 t ghqz oe# to output in high z 3 40 40 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. sampled, but not 100% tested. 4. see test configuration (figures 11 and 13), 2.7vC3.6v and 1.8vC2.2v standard test component values.
smart 3 advanced boot block Cbyte-wide e 40 preliminary address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 0605-015 figure 14. ac waveform: read operations
e smart 3 advanced boot block Cbyte-wide 41 preliminary table 16. ac characteristics: write operations (extended temperature) 1 load 50 pf # symbol parameter v cc 2.7v C3.6v 5 2.7v-3.6v 5 units prod 120 ns 150 ns notes min max min max w1 t phwl t phel rp# high recovery to we# (ce#) going low 600 600 ns w2 t elwl t wlel ce# (we#) setup to we# (ce#) going low 00ns w3 t wlwh t eleh we# (ce#) pulse width 90 90 ns w4 t dvwh t dveh data setup to we# (ce#) going high 370 70 ns w5 t avwh t aveh address setup to we# (ce#) going high 290 90 ns w6 t wheh t ehwh ce# (we#) hold time from we# (ce#) high 00ns w7 t whdx t ehdx data hold time from we# (ce#) high 30 0 ns w8 t whax t ehax address hold time from we# (ce#) high 20 0 ns w9 t whwl t ehel we# (ce#) pulse width high 30 30 ns w10 t vpwh t vpeh v pp setup to we# (ce#) going high 4 200 200 ns w11 t qvvl v pp hold from valid srd 4 0 0 ns t lock block unlock / lock delay 4, 6 200 200 ns notes: 1. read timing characteristics during program suspend and erase suspend are the same as during read-only operations. refer to ac characteristics during read mode. 2. refer to command definition table for valid a in (table6). 3. refer to command definition table for valid d in (table 6). 4. sampled, but not 100% tested. 5. see test configuration (figure 11 and 13), 2.7v C3.6v and 1.8vC2.2v standard test component values. 6. time t lock is required for successful locking and unlocking of all lockable blocks.
smart 3 advanced boot block Cbyte-wide e 42 preliminary addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w11 (note 1) (note 1) 0605-016 notes: 1. ce# must be toggled low when reading status register data. we# must be inactive (high) when reading status register data. a. v cc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. write read array command. figure 15. ac waveform: program and erase operations
e smart 3 advanced boot block Cbyte-wide 43 preliminary 7.1 reset operations ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plr h t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t 0605-17 figure 16. ac waveform: deep power-down/reset operation reset specifications v cc = 2.7 C3.6v symbol parameter notes min max unit t plph rp# low to reset during read (if rp# is tied to v cc , this specification is not applicable) 1,3 100 ns t plrh rp# low to reset during block erase or program 2,3 22 s notes: 1. if t plph is < 100 ns the device may still reset but this is not guaranteed. 2. if rp# is asserted while a block erase or byte program operation is not executing, the reset will complete within 100 ns. 3. sampled but not 100% tested.
smart 3 advanced boot block Cbyte-wide e 44 preliminary table 17. erase and program timings v pp = 2.7v v pp = 12v sym parameter notes typ 1 max 3 typ 1 max 3 unit t bwpb block program time (parameter) 2 .16 .48 .08 .24 sec t bwmb block program time (main) 2 1.23 3.69 .58 1.74 sec t whqv1 t ehqv1 program time 2 17 165 8 185 s t whqv2 t ehqv2 block erase time (parameter) 2 1 5.0 0.8 4.8 sec t whqv3 t ehqv3 block erase time (main) 2 1.8 8.0 1.1 7.0 sec t whrh1 t ehrh1 program suspend latency 3 5 10 5 10 s t whrh2 t ehrh2 erase suspend latency 3 5 20 6 12 s notes: 1. typical values measured at t a = +25c and nominal voltages. 2. excludes external system-level overhead. 3. sampled but not 100% tested.
e smart 3 advanced boot block Cbyte-wide 45 preliminary appendix a ordering information t e 2 8 f 1 6 0 b 3 t 1 2 0 package te = 40-lead tsop gt = 48-ball bga* csp product line designator for all intel flash products access speed (ns) (120, 150) product family b3 = smart 3 advanced boot block v cc = 2.7v - 3.6v v pp = 2.7v - 3.6v or 11.4v - 12.6v device density 016 = x8 (16-mbit) 008 = x8 (8-mbit) t = top blocking b = bottom blocking valid combinations 40-lead tsop 48-ball m bga* csp extended 16m te28f016b3t120 gt28f016b3t120 te28f016b3b120 gt28f016b3b120 te28f016b3t150 gt28f016b3t150 te28f016b3b150 gt28f016b3b150 extended 8m te28f008b3t120 gt28f008b3t120 TE28F008B3B120 gt28f008b3b120 te28f008b3t150 gt28f008b3t150 te28f008b3b150 gt28f008b3b150
smart 3 advanced boot block Cbyte-wide e 46 preliminary appendix b write state machine current/next states command input (and next state) current state sr.7 data when read read array (ffh) program setup (40/10h) erase setup (20h) erase confirm (d0h) program / erase susp. (b0h) program / erase resume (d0) read status (70h) clear status (50h) read id (90h) read array 1 array read array program setup erase setup read array read status read array read identifier program setup 1 status pgm. 1 program (command input = data to be programmed) program (not comp.) 0 status program pgm susp. to status program program (complete) 1 status read array program setup erase setup read array read status read array read identifier program suspend to status 1 status prog. susp. to array program suspend to array program program susp. to array program prog. susp. to status program suspend to array program suspend to array 1 array prog. susp. to array program suspend to array program program susp. to array program prog. susp. to status prog. susp. to array prog. susp. to array erase setup 1 status erase command error erase erase cmd. err. erase erase command error erase cmd. error 1 status read array program setup erase setup read array read status read array read identifier erase (not comp) 0 status erase ers. susp. to status erase erase (complete) 1 status read array program setup erase setup read array read status read array read identifier erase suspend to status 1 status erase susp. to array program setup erase susp. to array erase erase susp. to array erase erase susp. to status erase suspend to array erase. susp. to array 1 array erase susp. to array program setup erase susp. to array erase erase susp. to array erase erase susp. to status erase suspend to array read status 1 status read array program setup erase setup read array read status read array read identifier read identifier 1 id read array program setup erase setup read array read status read array read identifier 1. you cannot program 1s to the flash. writing ffh following the program setup will initiate the internal program algorithm of the wsm. although the algorithm will execute, array data is not changed. the wsm returns to read status mode without reporting any error. assuming v pp > v pplk writing a second ffh while in read status mode will return the flash to read array mode.
e smart 3 advanced boot block Cbyte-wide 47 preliminary appendix c access time vs. capacitive load (t avqv vs. c l ) access time vs. load capacitance derating curve 115 116 117 118 119 120 121 122 123 124 30 50 70 100 load capacitance(pf) access time(ns) smart 3 advanced boot block note: v ccq = 2.7v this chart shows a derating curve for device access time with respect to capacitive load. the value in the dc characteristics section of the specification corresponds to c l = 50 pf. note: 1. sampled, but not 100% tested
smart 3 advanced boot block Cbyte-wide e 48 preliminary appendix d architecture block diagram output multiplexer 8-kbyte parameter block 64-kbyte main block 64-kbyte main block 8-kbyte parameter block y-gating/sensing write state machine program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder power reduction control input buffer output buffer gnd v cc v pp ce# we# oe# rp# command user interface input buffer a 0 -a 20 dq 0 -dq 7 v ccq wp#
e smart 3 advanced boot block Cbyte-wide 49 preliminary appendix e additional information (1,2 ) order number document/tool 210830 1997 flash memory databook 290580 smart 3 advanced boot block word-wide 4-mbit (256k x 16), 8-mbit (512k x16), 16-mbit (1024k x16) flash memory family datasheet 292172 ap-617 additional flash data protection using v pp , rp# and wp# note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

▲Up To Search▲

Price & Availability of TE28F008B3B120

	To Download TE28F008B3B120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .